1. Field of the Invention
The present invention relates to a multiplexing system, provided in a line terminating unit of an ATM switch which accommodates a plurality of physical lines, which multiplexes fixed-length packets received over input lines on an output line connected to an ATM layer terminating apparatus, and more specifically to a multiplexing system adapted for an arrangement in which the bandwidth of the multiplexed output line is equal to or greater than the sum of the bandwidths of the input lines.
2. Description of the Related Art
In recent years, services haves become indispensable that uniformly handle various forms of communications, including not only transmissions of voice data and text data, but also transmissions of image data for which higher transmission or bit rates are required. As one of the major technologies that help to conduct such communications services, the ATM (asynchronous transfer mode) technique has been widely used.
In the ATM, information is transmitted on a cell-by-cell basis. Each cell consists of 48 octets of payload, and 5 octets of control information (including routing information) called the header.
Usually, ATM cells have their routes switched in a switch to which incoming lines and outgoing lines are connected. That is, upon receipt of a cell over an incoming line, the switch outputs it onto an outgoing line according to the routing information carried in its header. Thus, the cell can be routed to its destination.
The switch usually accommodates a large number of lines. However, it is usual that the number of ports (input ports or output ports) of a switching device involved in actual switching is considerably smaller than that of the lines accommodated, say, eight; this is because high-speed processing is achieved by taking advantage of statistical multiplexing. To input incoming cells received over the many input lines into the switching device, therefore, it is required to multiplex the incoming cells. Methods of multiplexing incoming lines include time-division multiplexing, statistical multiplexing, etc. Here, "multiplexing incoming lines" means, in this case, to multiplex cells coming from the incoming lines.
In the time-division multiplexing, the sum of bandwidths of input lines connected to a multiplexer is equal to or less than the bandwidth of the output line of the multiplexer, and each input line is assigned a portion of the bandwidth of the output line. The bandwidth assigned to each input line is referred to as a slot on the time base. Each cell inputted to the multiplexer over an input line is output onto the output line in a state where it is placed in the slot assigned to that input line.
The statistical multiplexing is generally applied to the arrangement in which the sum of the bandwidths of input lines of a multiplexer is greater than the bandwidth of the output line. The statistical multiplexing is a technique that employs the nature that the timing of the peak of traffic on each input line occurs at random and smoothes the peak of the total traffic by multiplexing such input lines.
The statistical multiplexing has an advantage that it can transmit large amounts of information with a low bandwidth. However, when congestion occurs, cells will be discarded. In order to avoid cells being discarded, the statistical multiplexing needs very complicated congestion control. With the time-division multiplexing, however, although the statistical multiplexing effect is not achieved, cells will not be discarded when they are multiplexed together. Thus, the time-division multiplexing is used for multiplexing incoming cells while avoiding cell congestion without complicated congestion control.
FIGS. 1A through 1C show block diagrams of a conventional time-division multiplexer. FIG. 1A is a block diagram of a WIRED-OR type multiplexer. Cells received over input lines 1 to N are respectively written into cell data storage FIFO memories 101-1 to 101-N. A controller 102 outputs read enable signals to the FIFO memories 101-1 to 101-N and gates 103-1 to 103-N in a cyclic manner. Upon receipt of a read enable signal from the controller 102, each of the FIFO memories 101-1 to 101-N reads a cell out. Upon receipt of the read enable signal from the controller 102, each of the gates 103-1 to 103-N outputs a cell read out from the corresponding FIFO memory onto the output line. The outputs of the respective gates 103-1 to 103-N are physically connected to a single line (output line). In this way, the input lines 1 to N are selected in a cyclic manner and thus cells received over the input lines are outputted in sequence onto the output line formed by connecting the gate outputs in a WIRED-OR connection.
When each of the FIFO memories is empty, it sends a FIFO empty indication signal to the controller 102 to make notification that no cell is stored. The controller 102 outputs no read enable signal to the FIFO memory that is outputting the FIFO empty indication signal.
FIG. 1B is a block diagram of a MUX type multiplexer. This type of multiplexer is equipped with a selector 105 on the output side of the FIFO memories 101-1 to 101-N. A controller 104 outputs a read enable signal to each of the FIFO memories in a cyclic manner and outputs a select signal to the selector 105. As with the WIRED-OR type multiplexer, each of the FIFO memories is responsive to a read enable signal to output a cell. The selector 105 selects an input line specified by the select signal to output a cell received over the selected input line onto the output line. In this way, each of the input lines 1 to N is selected in a cyclical manner and a cell received over the selected input line is sent over the output line.
The conventional techniques have the following drawbacks. In the WIRED-OR type, increasing the number of input lines results in an increase in the load capacitance associated with the output line connected in a WIRED-OR connection, causing rounding of pulse waveforms. As a result, cells from different input lines will collide with one another, making high-speed processing difficult.
In the MUX type, on the other hand, the selector 105 is installed independently of the circuits associated with the input lines (the FIFO memories, etc); thus, the multiplexer cannot flexibly adapt itself to a change in the number of the input lines. In addition, the MUX type multiplexer has a drawback that, when a large number N of input lines are divided into K groups of M lines (N=M.times.K) and an LSI is used to service each group of M input lines as shown in FIG. 1C, the multiplexing of N inputs sill require an additional LSI to combine the outputs of the K LSIs into a multiplexed signal.